1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to an improvement of a bit line precharging circuit in a dynamic random access memory (DRAM) having a hierarchical bit line structure.
2. Description of the Background Art
In general, a DRAM having the so-called hierarchical bit line structure has been proposed for the purpose of implementing a high storage capacity with a small chip area. In this DRAM, a plurality of subbit line pairs are provided in correspondence to one main bit line pair, and each subbit line pair is connected to the main bit line pair through two selection transistors. For example, Japanese Patent Laying-Open No. 60-234296 (1985) discloses a technique of connecting only subbit line pairs which are provided in a selected block to a main bit line pair.
Also in the DRAM having such a hierarchical bit line structure, it is necessary to precharge the main bit line pair and the subbit line pairs to a prescribed precharging potential (intermediate potential Vcc/2) in advance of data reading. If only one precharging circuit is simply provided in correspondence to one main bit line pair, however, a considerable time is required for the potentials of the subbit line pairs to reach the prescribed precharging potential, since the precharging potential is supplied to the subbit line pairs through the main bit line pair and the selection transistors. Further, subbit line pairs provided in a non-selected block are cut off from the main bit line pair to be brought into electrically floating states, and hence the potentials thereof are reduced in a non-selected period even if the subbit line pairs are precharged to the prescribed precharging potential. Therefore, the main bit line pair and the subbit line pairs must be precharged every time the latter are connected to the former. The aforementioned Japanese Patent Laying-Open No. 60-234296 neither discloses nor suggests a method of precharging the main bit line pair and the subbit line pairs.